Several types of memory devices, such as Flash memories, use arrays of memory cells for storing data. Each memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels. As an example, a Triple-Level Cell (TLC) device, stores three bits per cell using eight programming levels.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,” Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Some storage schemes store data at a density having a non-integer number of bits per memory cell. For example, U.S. Pat. No. 7,071,849, whose disclosure is incorporated herein by reference, describes fractional-bit systems that allow increments of the number of states per cell by as little as one between product generations. Since the number of states per cell is not an integer power of two, the number of bits per cell takes a fractional value. Cells are typically decoded in units of word, and the system efficiency can be optimized by adjusting the word-width.
As another example, U.S. Pat. No. 6,646,913, whose disclosure is incorporated herein by reference, describes a method for storing and reading data in a multilevel nonvolatile memory having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in the same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading the stored data word in the same clock cycle.
The method described in U.S. Pat. No. 7,167,109, whose disclosure is incorporated herein by reference, allows increments of the number of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of two, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in units of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.
U.S. Pat. No. 7,742,335, whose disclosure is incorporated herein by reference, describes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method further includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.
U.S. Pat. No. 7,848,142, whose disclosure is incorporated herein by reference, describes methods, devices, modules, and systems for programming memory cells that can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.
U.S. Pat. No. 7,420,841, whose disclosure is incorporated herein by reference, describes a memory device and a method of operating a memory device. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2n with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2n combinations of the set of combined states into n two-level data bits.